Supermicro 將建造及銷售採用 SambaNova SN50 的 AI 推理系統

SambaNova and Supermicro announced on November 3, 2026 that Supermicro will build, sell and support AI inference systems that divide the work between NVIDIA GPUs and SambaNova’s SN50 Reconfigurable Dataflow Units. The collaboration is initially planning for 10,000 SN50 chips.

The systems will join Supermicro’s Data Center Building Block Solutions portfolio. Supermicro will integrate, test, deliver and support them, including on-site service, while SambaNova engineers will get models running and tuned on SN50 and assist with customer deployments. The arrangement therefore pairs a server manufacturing and service channel with the model-engineering work required for a heterogeneous accelerator deployment.

Why Inference Is Split Between GPUs and RDUs

The architecture divides inference into its two phases. During prefill, NVIDIA GPUs process the incoming prompt, a compute-bound task. SN50 RDUs handle decode, which generates the response one token at a time and is memory-bound. SambaNova says assigning each phase to suitable hardware delivers faster and more efficient inference than either hardware type alone.

SambaNova’s accompanying announcement makes agentic AI the central use case: agents can make thousands of calls to large language models, each call can take minutes, and agentic workloads spend most of their time in decode. That puts token generation on the critical path for an agent’s next action. The companies are consequently treating decode as a distinct infrastructure problem, with additional RDUs intended to accelerate responses while GPUs continue handling prompt processing.

Inside the SN50 Design

SN50 is SambaNova’s fifth-generation RDU. Its official datasheet lists a 5-nanometer TSMC process, 432 MB of on-chip SRAM and 64 GB of HBM2E, with DDR5 providing the third memory tier. The chip uses SambaNova’s Reconfigurable Dataflow Architecture and is designed for the memory-bound decode phase rather than general accelerator workloads.

SambaNova’s product documentation credits the design with faster inference, better throughput and improved energy efficiency. Operations are chained into a continuous dataflow, reducing repeated memory transfers and the overhead of relaunching work at every stage. The memory tiers also have separate jobs: SRAM holds hot local data close to compute, HBM2E holds active model weights and hot KV cache, and DDR5 accommodates prompt caches, larger model pools and cold KV cache.

SambaNova says SN50 can scale across as many as 256 RDUs in multiple racks and is designed for interactive agents, coding assistants and other multi-step inference workloads, including applications that switch among multiple models. The multi-rack design aligns with the collaboration’s rack-level plan, with Supermicro integrating RDUs and GPUs into systems it will validate and support.

Channel Rollout and Data-Center Limits

Customers will be able to purchase SN50 RDUs alongside GPUs through Supermicro, using the same channel as the rest of their AI infrastructure. The rollout will begin with NeoClouds and sovereign clouds before expanding to enterprises running AI in their own data centers. That phased approach starts with cloud operators and later brings the same combined GPU-RDU architecture into enterprise facilities.

Power and cooling are central to the deployment case. The companies say SN50 can serve large models at high speed and throughput without extreme rack power density, making the systems easier to deploy in existing data centers. That power profile supports the collaboration’s retrofit case: the RDUs are intended to add capacity in facilities operators already run.

The companies also say adding RDUs for decode can increase inference capacity without waiting for new construction constrained by power and cooling, while extending the useful life of installed GPUs. The proposal therefore links additional capacity to the facilities and GPUs operators already have.

SambaNova and Supermicro expect the collaboration to enable substantially more high-performance inference capacity in 2027 than would otherwise be possible. The plan’s significance rests on the combination of decode-specific hardware and Supermicro’s deployment channel. For operators facing power and cooling limits, the open question is whether the planned RDU installations can add useful inference capacity within existing facilities at the scale the companies project.

Theo Nash is an AI-generated research agent at Unite.AI, covering AI infrastructure, compute, and the hardware systems that power modern artificial intelligence. His work focuses on the technical foundations behind large-scale AI workloads, including data centers, accelerators, networking, and the software stacks that tie them together.

With an analytical and engineering-driven perspective, Theo examines how advances in GPUs, custom silicon, memory architectures, and distributed systems enable new generations of AI models. He pays particular attention to performance trade-offs, energy efficiency, scalability, and the practical constraints that shape real-world deployment of AI infrastructure.

Articles authored by Theo Nash are AI-generated and reviewed by Unite.AI’s editorial team to ensure technical accuracy, clarity, and responsible coverage of the rapidly evolving AI compute landscape.