SK Hynix 公佈 H-TPU 控制器架構，採用逾 100 個小型處理器

SK Hynix Inc. has disclosed the architecture and performance of its Hynix Transaction Processing Unit (H-TPU), a small processor developed in-house for solid-state drives (SSDs).

The technology distributes repetitive tasks traditionally handled by general-purpose central processing units (CPUs) across more than 100 H-TPUs, significantly reducing power consumption and chip area.

​Koo In-je, a vice president at SK Hynix, stated at the International SoC Design Conference (ISOCC) 2026, held at Songdo Convensia in Incheon on Oct. 12, that general-purpose CPUs inside existing SSD controllers are reaching their limits in power consumption and chip area. SK Hynix developed the H-TPU to handle repetitive input/output (I/O) data-transfer paths more efficiently, he explained.

​The H-TPU is an ultra-lightweight programmable processor developed in-house by SK Hynix. It processes repetitive SSD operations, including read and write command processing, metadata management, and buffer control. Previously, general-purpose CPUs inside SSD controllers handled all these tasks. As SSD performance scaled up, the increasing workload required more CPU cores, which excessively expanded processor chip area and power consumption.

​Koo noted that Arm CPU cores commonly used in SSD controllers are overpowered for simple, repetitive tasks. These cores are optimized to process complex computations at high speed, meaning their deployment for simple SSD operations consumes unnecessary power and chip area. Their architecture is also ill-suited for splitting workloads into smaller tasks and distributing them across multiple processors.

​The H-TPU features a four-stage pipeline and a sequential execution structure suited for repetitive workloads. Unlike a monolithic CPU, multiple H-TPUs can be distributed across the controller and assigned specialized functions. The main general-purpose CPU is reserved for complex tasks, including error recovery, exception handling, and storage policy management.

​SK Hynix has integrated more than 100 H-TPUs into its SSD controller architecture. When an I/O request arrives, only the H-TPUs dedicated to the required functions are activated, while others remain in an idle state to save power. According to SK Hynix, a single H-TPU consumes approximately 2.5% (one-fortieth) of the power and occupies about 4% (one-twenty-fifth) of the chip area compared to a standard general-purpose CPU core.

​“SK Hynix decomposed the read and write processes of traditional SSD controllers into smaller tasks and structured the system so that numerous small H-TPUs process them in parallel,” Koo said. He added that the company has also developed software tools, including a dedicated compiler, to help engineers write specialized code more efficiently.

​SK Hynix plans to apply the H-TPU technology across multiple NAND flash product lines, starting with controllers for next-generation enterprise SSDs (eSSDs). The technology will subsequently be integrated into Storage Next, the company's next-generation storage architecture for AI, as well as high-bandwidth flash (HBF), which is scheduled for release next year.

​Storage Next is an architecture optimized for fine-grained data access required by modern AI models, handling data units down to 512 bytes—one-eighth the size of conventional 4-kilobyte (KB) units.