作者讓 Codex 設計 Raspberry Pi CM4 Mini-ITX I/O 載板，5V 電源通過 486 項分析條件

TL;DR: For two days, an AI coding agent (Codex) has been designing a Mini-ITX I/O board for the Raspberry Pi CM4 by driving KiCad from the command line in an inspect → fix loop. ERC is clean, the 5V rail passed 486 analysis conditions, routing has started — and the power design is fighting back. This is build log #1.

I'm building a carrier board for the Raspberry Pi Compute Module 4. Or, more accurately: I'm watching one get built.

The designer is an AI agent working through kicad-cli and scripted checks — running ERC/DRC, comparing schematic and PCB nets, doing DC analysis on the power rails, fixing what the checks flag, and re-running. My job is reading its inspection reports and looking at renders. It feels less like prompting a chatbot and more like supervising a very fast, very literal junior engineer who never sleeps and documents everything.

The spec is a bit unhinged

• Mini-ITX form factor, ATX 24-pin power
• DisplayPort ×1, HDMI ×1
• USB-A ×2, USB-C ×2
• A PCIe switch feeding PCIe slots ×2 + M.2 ×2

If you know the CM4, you see the problem immediately: the module exposes one PCIe Gen2 x1 lane, and DisplayPort isn't native to it. Cramming this into Mini-ITX, with ATX soft-power handling on top, is exactly the kind of dense, constraint-heavy problem I wanted to throw at the loop.

The loop's toolbox

Everything goes through the CLI and scripts, roughly like this:

kicad-cli sch erc board.kicad_sch            # electrical rule check
kicad-cli pcb drc board.kicad_pcb            # design rule check
# + custom scripts: net consistency, power DC analysis across tolerances

No GUI, no mouse. Just checks, fixes, and re-checks — hundreds of iterations.

The scoreboard after 2 days

• Schematic ERC: 0 errors, 3 warnings
• Schematic ↔ PCB net mismatches: 0
• CM4 5V rail DC analysis: 486 conditions (reference/resistor tolerance, temperature coefficient, input bias) → output range 4.909–5.092 V. Inside the CM4's 5V ±5% requirement, with ~0.16 V of margin on the low side
• Startup analysis with the manufacturer's power model: timed out twice. Still undetermined, and the loop says so plainly. I trust a tool more when it admits what it hasn't proven
• At placement stage: 1,464 unrouted segments, 244 DRC errors. Routing has now started, so those numbers are finally moving

An 8mm × 10mm drama

The moment that made me start this log is a clearance check in the power section. On the front copper, a signal trace (D4 TX N) has to pass the projection of the back-side MOSFET's drain pad — Q901, sitting next to the R900 current shunt. The drain is a high-current power net, so the loop projects the back-side pad onto the front view and routes the signal around it, checking clearance point by point.

Unglamorous, invisible work. Also the work that decides whether a board works at all.

Where it's losing (for now)

• IR drop. Under load, the power rails sag more than they should. The loop has started flagging it on its own
• The 1.1 V rail still drops too much
• Power sequencing for the expansion cards is unfinished — a board that boots the CM4 but browns out a PCIe card is a paperweight
• MOSFET selection for the power stage is still open. Those FETs set the Rds(on) losses, so the choice feeds straight back into the IR-drop problem. The loop is researching candidates right now

The silkscreen on the current layout literally reads "UNROUTED ENGINEERING DRAFT / DO NOT FABRICATE". Accurate.

Questions for people who've done this

If you've designed CM4 carrier boards:

1. How did you handle power sequencing for downstream PCIe devices?
2. What MOSFETs did you land on for the input power stage?

Genuinely collecting answers — the loop and I are still deciding, and I'd rather learn from your scars than earn my own.

Part 2 when routing finishes (or when the startup analysis finally completes instead of timing out — whichever comes first).