GSA Women’s Leadership Initiative 的 6 項觀察：AI 半導體競爭由晶片戰轉向系統戰

6 insights from the GSA Women’s Leadership Initiative: AI semiconductor industry trends turn the chip race into a systems race

For decades, the semiconductor industry competed on one thing: the individual chip. One of the biggest AI semiconductor industry trends now under way is the shift toward treating chips as components of much larger systems. Performance, cost and reliability are now determined across the package, the rack and the supply chain, not inside a single die.

That shift moves the hardest problems upstream. Packaging, connectivity, yield, sourcing and verification used to come after design, but now they shape it from the first day. AI is shortening development cycles at the same time as it adds to the complexity engineers have to manage. The next phase will be defined by how well companies coordinate across that whole system.

“I think the AI system is our new chips,” said Letizia Giuliano, vice president of product management and marketing at Qualcomm Technologies Inc. “If we were optimizing everything for the silicon in the past, now these days we’re optimizing everything for the system.”

Giuliano and other industry experts spoke with theCUBE Research’s John Furrier and co-host Alison Kosik at the GSA Women’s Leadership Initiative event in Palo Alto, California. The interviews covered AI semiconductor industry trends, optical interconnects, advanced packaging, AI-driven yield learning, physical AI, strategic sourcing and AI-assisted chip design.

Here are six standout insights from the event:

1. Connectivity overtakes compute as the bottleneck in AI infrastructure.

Moving data between chips, memory and racks now limits AI performance more than raw compute, according to Giuliano. At 200 gigabits per second per lane, half of the signal budget goes just to getting out of the package. That is pushing optical interconnect from rack-to-rack links into the rack, the blade and the package itself, with copper and optics in use side by side. Qualcomm has just launched High Bandwidth Compute, a low-power way to attach compute to memory that is tuned for tokens per watt. Building such products at hyperscale volume means product engineering has to join design-for-test, manufacturing and reliability planning early, explained Sophie Wang, senior director of product engineering at Marvell Technology Inc.

Check out theCUBE’s complete interview.

2. Advanced packaging moves from afterthought to system architecture.

The boundary of an AI system is shifting from the chip to the package, emphasized Nisha Ananthakrishnan, senior director of advanced packaging at Intel Corp. Intel uses its EMIB bridge technology to link chiplets and to scale packages from 3x to more than 10x form factors. Outsourced assembly and test providers are becoming system integrators, noted Patricia MacLeod, senior director of corporate communications and industry partnerships at Advanced Semiconductor Engineering Inc. She pointed to ASE’s VIPack platform, which supports technologies ranging from fan-out chip-on-substrate to co-packaged optics. Many of the chips AI depends on, such as power management chips and voltage regulators built at 12 to 28 nanometers, use mature nodes, added Tazrien Kamal, senior director of technology and innovation at GlobalFoundries Inc.

Watch the full interview from theCUBE.

3. AI-driven yield learning turns speed to volume into a competitive edge.

About 70% to 80% of the problems found when scaling up volume manufacturing could have been caught before tapeout, highlighted Preeti Prasher, chief operating officer of Stathera Inc. Using AI to analyze characterization, simulation and inline manufacturing data lets teams start new wafers before a bad lot reaches test. Adaptive testing also cuts test time. Lattice Semiconductor Corp. has released Lattice Prompt, its first AI design assistant, which turns a plain-language request into a field-programmable gate array design and recommends the best part for the form factor and cost, according to Iliana Chen, senior director of program management at Lattice. Demand from robotics and other markets has made volume Lattice’s biggest challenge, Chen noted.

See theCUBE’s full coverage.

4. Physical AI becomes a system-level challenge, not a chip war.

Physical AI is much broader than humanoid robots and covers any autonomous system that senses its surroundings, reasons and acts in the physical world, explained Gina Longoria, VP of external communications at Arm Ltd. The market is in its first inning, and no single company can build the architecture, security and safety standards it needs on its own, she stressed. Firmware is becoming the layer that ties GPUs, CPUs, network cards and Compute Express Link devices into one fleet-scale system, shared Lakshmi Ramagiri, partner for firmware engineering at Microsoft Corp. Security has to move beyond secure boot to continuous trust while a system is running, and the Open Compute Project and DMTF are the standards bodies to watch, Ramagiri added.

Don’t miss the full interview on theCUBE.

5. Strategic sourcing becomes a product decision as AI strains the supply chain.

Sourcing now goes well beyond negotiating prices and shapes product development, risk and customer experience, emphasized Alisa Wang, AVP of global planning and procurement at Credo Technology Group Holding Ltd. Because AI-driven demand can change within a year, suppliers have to be treated as strategic partners that receive product roadmaps early, she noted. Leading-edge logic capacity at Taiwan Semiconductor Manufacturing Co. Ltd. is the tightest constraint, followed by packaging, specialty materials and critical equipment. In response, Credo is qualifying second-source suppliers and spreading its manufacturing footprint across more regions. Stathera’s Prasher highlighted dual sourcing for key segments and using supplier feedback during new product introduction to develop lower-cost products together.

Hear the full story on theCUBE.

6. AI agents compress chip design as development cycles shrink to six to nine months.

AI is moving from a productivity assistant to a built-in part of electronic design automation flows, explained Rimi Dasgupta, chief of staff for product management and markets at Synopsys Inc., and Vidya Neerkundar, director of product management at Siemens Digital Industries Software. Synopsys has seen verification closure on register-transfer-level designs accelerate as much as 50-fold and debug time drop by 40%, according to Dasgupta. Demand for workload-optimized custom silicon has also cut development cycles from 18 months to six to nine months. AI is probabilistic, but chips must be deterministic, so Synopsys pairs AI with multiphysics solvers from its Ansys acquisition and is working with OpenAI Group PBC on a dedicated GPT-Synopsys model. Multi-die design is the next big shift as chips hit reticle limits, Neerkundar noted.

Catch the complete conversation on theCUBE.

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