SEMI稱橋接技術將引領下一代大尺寸半導體封裝

Beth Keser, vice president of SEMI’s APHI technology community, speaks during a briefing. (Photo: THE ELEC)

SEMI, the global semiconductor industry association, announced at a media briefing ahead of Semicon West 2026 in San Francisco on Oct. 12 that bridge technology will drive the next generation of large-format semiconductor packaging.

Beth Keser, vice president of SEMI’s Advanced Packaging and Heterogeneous Integration (APHI) technology community, said chip-to-chip connections using silicon interposers face significant manufacturing limitations in large-format packages as silicon interposers hit production constraints. “In the near term, heterogeneous integration packaging using bridges will lead the market,” she said.

Bridge packaging embeds small dies in a flip-chip ball-grid-array (FC-BGA) substrate to connect semiconductor chips. Instead of using a large silicon interposer, the structure places bridges only where high-density wiring between chips is required. Silicon is widely used as the bridge material.

As the industry seeks to boost the performance of artificial intelligence (AI) semiconductors, 2.5D packaging — which integrates multiple graphics processing units (GPUs), high-bandwidth memory (HBM), and other components in a single package — has become more common. Traditionally, multiple chips have been mounted on a silicon interposer, which supports fine-pitch wiring, and then bonded to an organic FC-BGA substrate.

The challenge is that silicon interposer manufacturing becomes less efficient as the number of integrated chips rises and package dimensions increase. Silicon interposers are made from 300-millimeter (mm) circular silicon wafers. When packages grow to 100-by-100 mm or larger, the number of interposers that can be produced from one wafer falls to four or fewer. The circular shape of the wafer leaves areas around its edges unsuitable for producing rectangular interposers.

“AI server semiconductor packages are getting bigger,” Keser said. “Intel central processing unit (CPU) packages used to be around 45-by-45 mm, but now they are exceeding 100-by-100 mm and reaching 120-by-120 mm.”

Silicon bridges have emerged as an alternative. Intel has used its Embedded Multi-die Interconnect Bridge (EMIB) structure in mass production since 2017. Taiwan Semiconductor Manufacturing Co. (TSMC) has adopted its Chip-on-Wafer-on-Substrate-Local (CoWoS-L) package, which embeds local silicon bridges in a redistribution-layer (RDL) interposer, starting with Nvidia’s Blackwell platform. Outsourced semiconductor assembly and test (OSAT) companies ASE and Amkor Technology are also developing bridge-based technologies, called Fan-Out-Chip-on-Substrate-Bridge (FoCoS-B) and S-Connect, respectively.

There are also efforts to use organic materials for bridges. These approaches build RDLs using photosensitive dielectric (PID), which can support finer wiring than Ajinomoto Build-up Film (ABF), the material used to create interlayer signal pathways in FC-BGA substrates. A separately fabricated high-density organic bridge is then embedded in the top of the FC-BGA substrate to connect chips. Samsung Electro-Mechanics and Qualcomm are jointly developing this approach.

Keser said Japan’s Shinko Electric Industries is also developing an organic-material bridge-interposer technology called integrated Thin film High density Organic Package (i-THOP). “It could be suitable for products that need lower manufacturing costs than through-silicon-via (TSV) bridges,” she said.

Keser also forecast that larger packages would accelerate the adoption of glass substrates. “Two years ago, I would have expected glass substrates to arrive around 2030, but packages are growing so quickly that I now expect adoption around 2028,” she said. “One or two leading companies will likely adopt the technology first, followed by other manufacturers.”

SEMI launched its APHI technology community in July 2023 as advanced packaging became increasingly important. The group discusses technology development and standardization for advanced packaging, including heterogeneous integration. Keser, who leads APHI, has more than 30 years of experience in advanced packaging at companies including Motorola, Qualcomm, and Intel.

According to THE ELEC, the briefing took place on the sidelines of Semicon West 2026 in San Francisco.