3D DRAM 與 4F² 縮放：電容成為瓶頸

Memory is the part of the computer that everyone assumes will get cheaper. For thirty years it did, at roughly 30% per year in cost per bit, and every software architecture written in that period quietly depends on the assumption continuing. It is not continuing, and the reason is not demand. It is a capacitor.

A DRAM cell is one transistor and one capacitor. The capacitor stores the bit as charge, and it must hold enough charge that a sense amplifier can still distinguish a one from a zero after the leakage of a refresh interval. As the cell shrinks in area, the capacitor must keep roughly the same capacitance, which means it must get taller while getting narrower. That is the whole problem, stated in one sentence.

Part One: What 4F² buys and what it costs

The current mainstream cell is 6F², where F is the minimum feature size. A 4F² cell arranges the transistor and capacitor differently, typically with a vertical access transistor, and recovers about a third of the area. On paper that is the cheapest route to more bits per wafer, because it uses the existing planar process flow with a redesigned layout rather than a new stack.

In practice, 4F² moves the difficulty from lithography to the capacitor. A smaller footprint means a taller capacitor for the same capacitance, and the aspect ratio, the ratio of height to width, is already above 50 to 1 at the leading node. Etching a hole that deep and that narrow, then filling it uniformly with a high-k dielectric and a metal electrode, is one of the hardest unit processes in manufacturing. Every increment in aspect ratio costs yield, and yield is the only currency that matters.

The second cost is the peripheral circuit. A 4F² cell needs a vertical transistor, which needs a different integration scheme, which means the periphery and the array no longer share the same thermal budget. That is a process integration problem that shows up as a new defect mechanism rather than as a line item.

Part Two: What 3D DRAM actually means

The alternative branch stacks the array. Instead of making the cell smaller, you make more layers of cells, the way NAND flash did when planar scaling ran out. The analogy is attractive and the physics is much harder, because NAND stores charge in a floating gate that tolerates a slow, noisy read, while DRAM must be read and rewritten in nanoseconds by a sense amplifier that sits at the edge of the array.

Two architectures are in discussion. The first stacks the array above the periphery, using the periphery's silicon area for the logic and putting the memory on a separate layer bonded on top. That buys area without changing the cell, and it is the version most likely to ship first, because it reuses the existing cell design and the existing sense amplifier design. The second builds a genuinely three-dimensional array with vertical bit lines and horizontal word lines, which is a much larger change and is still in the research stage.

The first version has a hidden cost that deserves attention: heat. DRAM refresh gets worse when the array is hot, and stacking a memory array on top of a logic die puts the hottest silicon underneath the memory. Thermal management becomes a design constraint, not a packaging afterthought.

Part Three: Why this matters beyond the fab

The cost per bit of DRAM sets the shape of software. When memory was getting cheaper every year, the winning strategy was to spend memory to save engineering time: cache everything, keep sessions in RAM, load the whole index. That is why so much of the modern stack assumes a machine with 64 or 128 gigabytes and treats that as small.

If cost per bit flattens, the economics invert. Spending memory becomes a real cost, and the architectures that win are the ones that use memory carefully: streaming, tiering, compression, and, increasingly, offloading to storage that is slower but far cheaper per byte. That is not a hypothetical. It is already happening in inference serving, where the KV cache has become the dominant memory consumer and every serving stack now has an offload path.

There is a social version too. The reason a smartphone can do on-device speech recognition, and a cheap laptop can run a local model, is that memory got dense and cheap enough. If density growth slows, the devices that benefit first are the expensive ones, and the gap between what a flagship can do locally and what a budget device can do locally widens. That gap is a policy question disguised as a process node.

Part Four: The industry structure consequence

Three companies make almost all DRAM. A technology transition that requires a new etch tool, a new dielectric stack, and a new bonding step raises the capital intensity of staying at the leading edge, which favours the incumbents and raises the barrier for anyone trying to enter. It also lengthens the time between node introductions, which changes the buying rhythm: customers who used to plan on a two-year cadence now plan on three.

For the equipment industry, the interesting part is that both branches need more deposition and more etch, not less. Whether the industry goes 4F² or stacked, the number of process steps per wafer goes up. The companies that sell the tools win either way, which is a useful reminder that in a standards war, the safest position is often selling to both sides.

Part Five: A market sizing sanity check

DRAM revenue runs at roughly 90 to 110 billion dollars a year across the cycle, with bit growth historically in the high teens and price per bit falling 20 to 30% annually. If the cost curve flattens to 10% per year, the same bit demand produces a market that grows faster in dollars, not slower. That is the paradox of a maturing memory industry: slower cost reduction means higher revenue for the same physical output, and higher revenue means more capital available to solve the next process problem.

The forecast that matters is not the revenue number. It is the crossover point where the industry stops pricing per bit and starts pricing per watt and per cubic millimetre, which is already how HBM is sold. When commodity DRAM starts to be sold that way too, the memory business stops being cyclical and starts being a capacity business, which is a very different kind of company.

The comparison that matters

4F² scaling buys density with process risk concentrated in one heroic step: the capacitor etch. 3D DRAM buys density with process risk spread across bonding, thermal management and a new array architecture. The first is a bet that the equipment industry can keep delivering aspect ratios; the second is a bet that packaging can carry the load.

Both are being pursued at the same time by the same companies, which tells you that nobody is confident. The practical consequence for anyone building systems is to stop assuming 30% annual cost reduction, and to design software that treats memory as a resource to be managed rather than a resource to be spent.

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